View THC63LVDM83D_9051182.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 1 thine electronics, inc. security e thc63 lvdr 84 c 24 b it color lvds receiver ( rising edge strobe output ) general description t h e thc63 lvdr 84c receiver supports wide temperature range as - 40 to +85 ? c , and wide frequency range as 8 to 112mhz . the thc63 lvdr 84c converts the four lvds data streams back into 24bits of lvcmos data with rising edge clock . at a transmit clock frequency of 112 mhz, 24bits of rgb data and 4bits of timing and con trol data (hsync, vsync, de, etc. ) are transmitted at an effective rate of 3.1 g bps . application ? medium and s mall s ize p anel ? secu rity camera ? multi function printer ? machine vision ( frame grabber board ) ? medical equipment monitor features ? 1 : 7 lvds to lv cmos de s e rializer ? operating temperature range : - 4 0 to + 85 ? c ? no special start - u p sequence required ? spread spectrum clocking t olerant up to 100khz f requency m odulation and +/ - 2.5% d eviations ? pixel c lock r ange: 8 to 112 mhz ? 56 pin tssop package ? power d own m ode ? rising edge strobe output ? e u rohs compliant recommended lvds transmitter ics ? THC63LVDM83D ? thc63lvdm87 block diagram figure 1 . block diagram p l l r a + / - r b + / - r c + / - r d + / - / p d w n 7 l v d s i n p u t s ( 5 6 t o 7 8 4 m b p s / c h ) r a 0 - 6 c l k o u t ( 8 t o 1 1 2 m h z ) l v c m o s o u t p u t s t h c 6 3 l v d r 8 4 c r b 0 - 6 r c 0 - 6 r d 0 - 6 r c l k + / - ( 8 t o 1 1 2 m h z ) 7 7 7 l v d s t o l v c m o s 1 : 7 d e s e r i a l i z e r
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 2 thine electronics, inc. security e pin diagram f igure 2 . pin diagram pin description pin name pin # direction type description r a+, r a - 10 , 9 input lvds lvds data inputs r b+, r b - 12 , 11 r c+, r c - 16 , 15 r d+, r d - 20 , 19 r clk+, r clk - 18 , 17 lvds clock inputs ra0 ~ ra6 27, 29, 30, 32, 33, 35, 37 output lv cmos pixel data outputs rb0 ~ rb6 38, 39, 43, 45, 46, 47, 51 rc0 ~ rc6 53, 54, 55, 1, 3, 5, 6 rd0 ~ rd6 7, 34, 41, 42, 49, 50, 2 clkout 26 pixel clock output /pdwn 25 input h : normal operation l : power down ( a ll outputs are pulled to ground) vcc 31, 40, 48, 56 - power power su pply pins for lvcmos outputs and digital circuitry gnd 4, 28, 36, 44, 52 ground pins for lvcmos outputs and digital circuitry lvds vcc 13 power supply pins for lvds inputs lvds gnd 8, 14, 21 ground pins for lvds inputs pll vcc 23 power supply pins for pll circuitry pll gnd 22, 24 ground pins for pll circuitry table 1 . pin description 1 5 6 2 5 5 3 5 4 4 5 3 5 5 2 6 5 1 7 5 0 8 4 9 9 4 8 1 0 4 7 1 1 4 6 1 2 4 5 1 3 4 4 1 4 4 3 1 5 4 2 1 6 4 1 1 7 4 0 1 8 3 9 1 9 3 8 2 0 3 7 2 1 3 6 2 2 3 5 2 3 3 4 2 4 3 3 2 5 3 2 2 6 3 1 2 7 3 0 2 8 2 9 r c 3 r d 6 r c 4 g n d r c 5 r c 6 r d 0 l v d s g n d r a - r a + r b - r b + l v d s v c c l v d s g n d r c - r c + r c l k - r c l k + r d - r d + l v d s g n d p l l g n d p l l v c c p l l g n d / p d w n c l k o u t r a 0 g n d v c c r c 2 r c 1 r c 0 g n d r b 6 r d 5 r d 4 v c c r b 5 r b 4 r b 3 g n d r b 2 r d 3 r d 2 v c c r b 1 r b 0 r a 6 g n d r a 5 r d 1 r a 4 r a 3 v c c r a 2 r a 1
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 3 thine electronics, inc. security e absolute maximum ratings parameter min max unit supply voltage ( vcc, lvds vcc, pll vcc ) - 0.3 +4.0 v lvcmos input voltage - 0.3 vcc + 0.3 v lvcmos output voltage - 0.3 vcc + 0.3 v lvds input pin - 0.3 vcc + 0.3 v junction temperature - +125 ? c storage temperature - 55 +150 ? c reflow peak temperature - +260 ? c reflow peak temperature time - 10 sec maximum power dissipation @+25 ? c - 1. 9 w table 2 . absolute maximum rating s recommended operating conditions symbol parameter min typ max unit vcc33 all supply voltage (vcc, lvds vcc, pll vcc) 3.0 - 3.6 v ta operating ambient temperature - 40 +25 +85 ? c pclk rclk and clkout clock frequency 8 - 112 mhz table 3 . recommended operating conditions absolute m aximum r atings are those value s beyond which the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of e lectrical characteristics table4, 5, 6, 7 specify conditions for device operation. absolute m axi mum r ating value also include s behavior of overshooting and undershooting.
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 4 thine electronics, inc. security e equivalent lvds in put schematic diagram figure 3 . lvds in put schematic diagram output control /pdwn rclk +/ - input lvcmos output h valid clock active clock & data h invalid clock unfixed clock & data h open or hi - z all low l dont care all low table 4 . lvcmos output data control l v d s + l v d s - a m p c m p l v d s v c c l v d s v c c o u t p u t c o n t r o l l v d s v c c
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 5 thine electronics, inc. security e power consumption over recommended operating supply and temperature range unless otherwise specified symbol parameter conditions typ* max unit i rccg lvds receiver operating current gray scale pattern 16 (fig.4) cl=8pf, pclk =65mhz, vcc 33 =3.3v 55 70 ma cl=8pf, pclk =112mhz, vcc 33 =3.3v 90 110 ma i rccw lvds receiver operating current worst case pattern(fig.5) cl=8pf, pclk =65mhz, vcc 33 =3.3v 90 110 ma cl=8pf, pclk =112mhz, vcc 33 =3.3v 130 160 ma i rccs lvds receiver power down current /pdwn=l - 500 a *typ values are at the conditions of t a = +25 o c table 5 . power consumption 16 grayscale pattern figure 4 . 16 grayscale pattern worst case pattern figure 5 . worst case pattern c l k o u t r a 3 , r b 4 , r c 5 r a 2 , r b 3 , r c 4 r a 1 , r b 2 , r c 3 r a 0 , r b 1 , r c 2 t a 4 - 6 , t b 0 / 5 / 6 t c 0 / 1 / 6 , t d 0 - 2 t d 3 - 6 s t e a d y s t a t e l o w s t e a d y s t a t e h i g h c l k o u t r x 0 - 6 x = a , b , c , d
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 6 thine electronics, inc. security e electrical characteristics lvds receiver dc specifications over recommended operating supply and temperature range unless otherwise specified symbol parameter conditions min typ* max unit v th differential input high threshold rl=100, vic=+1.2v - - 100 mv v tl differential input low threshold - 100 - - mv i in input current v in =+2.4 / 0v lvds vcc = 3.6v - - ? 30 ? a table 6 . lvds receiver dc specifications lvcmos dc specifications over recommended operating supply and temperature range unless otherwise specified symbol parameter conditions min typ max unit v ih high level input voltage - 2.0 - vcc v v il low level input voltage - gnd - 0.8 v v oh high level output voltage i oh = - 4ma (data) i oh = - 8ma (clock) 2.4 - - v v ol low level output voltage i ol =4ma (data) i ol =8ma (clock) - - 0.4 v i in input current gnd ? v in ? vcc - - ? 10 ? a table 7 . lvcmos dc specifications lvcmos output load limitation the output load is limited so that the junction temperature does not exceed 125 ? c. figure 6 . lvcmos output load limitation 0 . 0 5 . 0 1 0 . 0 1 5 . 0 2 0 . 0 2 5 . 0 8 2 8 4 8 6 8 8 8 1 0 8 c l k o u t [ m h z ] o u t p u t l o a d [ p f ] t a = 7 0 t a = 8 5
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 7 thine electronics, inc. security e switching characteristics over recommended operating supply and temperature range unless otherwise specif ied symbol parameter min typ* max unit t rcp rclk and clkout transition time 8.92 t 125 ns t rch lvcmos clkout high time - t/2 - ns t rcl lvcmos clkout low time - t/2 - ns t rcd rclk in to clkout delay - (3/14+3) t - ns t rs lvcmos data setup to clkout 0.35 t - 0.3 - - ns t rh lvcmos data hold from clkout 0.45 t - 1.6 - - ns t tlh lvcmos low to high transition time - 0.7 1.0 ns t thl lvcmos high to low transition time - 0.7 1.0 ns t sk lvds receiver skew margin pclk =65mhz - 0.55 - 0.55 ns pclk =112mhz - 0.25 - 0.25 t rip1 lvds input data position0 - t sk 0.0 + t sk ns t rip0 lvds input data position1 t/7 - t sk t/7 t/7+ t sk ns t rip6 lvds input data position2 2t/7 - t sk 2t/7 2t/7+ t sk ns t rip5 lvds input data position3 3t/7 - t sk 3t/7 3t/7+ t sk ns t rip4 lvds input data position4 4t/7 - t sk 4t/7 4t/7+ t sk ns t rip3 lvds input data position5 5t/7 - t sk 5t/7 5t/7+ t sk ns t rip2 lvds input data position6 6t/7 - t sk 6t/7 6t/7+ t sk ns t rpll phase lock loop set - - 10.0 ms *typ values are at the conditions of vcc 33 =3.3v and t a = +25 o c table 8 . lvcmos & lvds receiv er ac specifications
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 8 thine electronics, inc. security e ac timing diagrams lvds input figure 7 . lvds input data position lvcmos output figure 8 . lvcmos output load and trans ition time figure 9 . lvcmos output setup and hold time r c l k + r a + / - r a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r b 6 r b 5 r b 4 r b 3 r b 2 r b 1 r b 0 r c 6 r c 5 r c 4 r c 3 r c 2 r c 1 r c 0 r d 6 r d 5 r d 4 r d 3 r d 2 r d 1 r d 0 t r i p 6 t r i p 5 t r i p 4 t r i p 3 t r i p 2 t r i p 1 t r i p 0 ( d i f f e r e n t i a l ) r b + / - r c + / - r d + / - n e x t c y c l e v d i f f = 0 v v d i f f = 0 v t r c p c u r r e n t c y c l e p r e v i o u s c y c l e n o t e : v d i f f = ( r c l k + ) - ( r c l k - ) t t l h 8 0 2 0 8 0 2 0 t t h l c l = 8 p f c l k o u t t r c p t r c h t r c l v c c / 2 v c c / 2 v c c / 2 t r s t r h r a 0 - r a 6 r b 0 - r b 6 r c 0 - r c 6 r d 0 - r d 6 v c c / 2 v c c / 2 v a l i d d a t a
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 9 thine electronics, inc. security e input to output delay figure 10 . input clock to output clock delay time phase lock loop set time figure 11 . pll lock loop set time r c l k + v d i f f = 0 v v c c / 2 t r c d c l k o u t n o t e : v d i f f = ( r c l k + ) - ( r c l k - ) v c c 3 3 3 . 0 v r c l k + / - / p d w n v c c / 2 c l k o u t v c c / 2 t r p l l
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 10 thine electronics, inc. security e application note display data mapping example transmitter pin vesa format jeida format receiver pin 6bit (18bpp) 8bit (24bpp) 6bit (18bpp) 8bit (24bpp) ta0 r0 r0 r2 r2 ra0 ta1 r1 r1 r3 r3 ra1 ta2 r2 r2 r4 r4 ra2 ta3 r3 r3 r5 r5 ra3 ta4 r4 r4 r6 r6 ra4 ta5 r5 r5 r7 r7 ra5 ta6 g0 g0 g2 g2 ra6 tb0 g1 g1 g3 g3 rb0 tb1 g2 g2 g4 g4 rb1 tb2 g3 g3 g5 g5 rb2 tb3 g4 g4 g6 g6 rb3 tb4 g5 g5 g7 g7 rb4 tb5 b0 b0 b2 b2 rb5 tb6 b1 b1 b3 b3 rb6 tc0 b2 b2 b4 b4 rc0 tc1 b3 b3 b5 b5 rc1 tc2 b4 b4 b6 b6 rc2 tc3 b5 b5 b7 b7 rc3 tc4 hsync hsync hsync hsync rc4 tc5 vsync vsync vsync vsync rc5 tc6 de de de de rc6 td0 - r6 - r0 rd0 td1 - r7 - r1 rd1 td2 - g6 - g0 rd2 td3 - g7 - g1 rd3 td4 - b6 - b0 rd4 td5 - b7 - b1 rd5 td6 - n/a - n/a rd6 note : use ta to tc channels and open td channel for 6bit application . table 9 . data mapping for vesa & jeida rgb color format
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 11 thine electronics, inc. security e system connection example figure 12 . connecti on example with jeida format c l k i n r 2 r 3 r 4 r 5 r 6 r 7 g 2 g 3 g 4 g 5 g 6 g 7 b 2 b 3 b 4 b 5 b 6 b 7 h s y n c v s y n c d e r 0 r 1 g 0 g 1 b 0 b 1 c l k i n t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 t a 6 t b 0 t b 1 t b 2 t b 3 t b 4 t b 5 t b 6 t c 0 t c 1 t c 2 t c 3 t c 4 t c 5 t c 6 t d 0 t d 1 t d 2 t d 3 t d 4 t d 5 t d 6 / p d w n / p d w n r s v c c 3 3 r / f g n d v c c v c c 3 3 l v d s g n d r a - r a + r b - r b + l v d s v c c r c - r c + r c l k - r c l k + r d - r d + p l l g n d p l l v c c t a - t a + t b - t b + t c - t c + t c l k - t c l k + t d - t d + f e r r i t e b e a d f e r r i t e b e a d 0 . 1 u f 0 . 0 1 u f t h c 6 3 l v d m 8 3 d p c b ( t r a n s m i t t e r ) 0 . 1 u f 0 . 1 u f 0 . 0 1 u f c l k o u t r a 0 r a 1 r a 2 r a 3 r a 4 r a 5 r a 6 r b 0 r b 1 r b 2 r b 3 r b 4 r b 5 r b 6 r c 0 r c 1 r c 2 r c 3 r c 4 r c 5 r c 6 r d 0 r d 1 r d 2 r d 3 r d 4 r d 5 r d 6 l v d s g n d p l l g n d p l l v c c 0 . 1 u f 0 . 0 1 u f l v d s v c c 0 . 1 u f 0 . 0 1 u f / p d w n / p d w n c l k o u t r 2 r 3 r 4 r 5 r 6 r 7 g 2 g 3 g 4 g 5 g 6 g 7 b 2 b 3 b 4 b 5 b 6 b 7 h s y n c v s y n c d e r 0 r 1 g 0 g 1 b 0 b 1 o p e n t h c 6 3 l v d f ( r ) 8 4 c g n d v c c v c c 3 3 f e r r i t e b e a d f e r r i t e b e a d 0 . 1 u f 0 . 0 1 u f p c b ( r e c e i v e r ) 1 0 0 o h m 1 0 0 o h m 1 0 0 o h m 1 0 0 o h m 1 0 0 o h m g n d g n d 0 . 0 1 u f 1 0 0 o h m p a i r c a b l e o r p c b t r a c e
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 12 thine electronics, inc. security e note s 1) cable connection and disconnection do n o t connect and disconnect the lvds cable, when the power is supplied to the system. 2) gnd connection con nect each gnd of the pcb which lvds - tx and thc63 lvdr 84c on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 3) multi drop connection multi drop connection is not recommended. figure 13 . multi drop connection 4) asynchronous use asynchronous using such as following systems is not recommended. figure 14 . asynchronous u se t h c 6 3 l v d r 8 4 c l v d s - t x t h c 6 3 l v d r 8 4 c r c l k + r c l k - t h c 6 3 l v d r 8 4 c t h c 6 3 l v d r 8 4 c l v d s - t x l v d s - t x i c c l k o u t c l k o u t d a t a d a t a i c r c l k + r c l k - r c l k + r c l k - c l k o u t d a t a d a t a t h c 6 3 l v d r 8 4 c t h c 6 3 l v d r 8 4 c i c r c l k + r c l k - r c l k + r c l k - c l k o u t d a t a d a t a i c
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 13 thine electronics, inc. security e package figure 15 . package d iagram
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 14 thine electronics, inc. security e reference land pattern figure 16 . reference of land pattern the recommendation mount ing method of thine device is reflow soldering. t he reference pattern is using the calculation result on condition of reflow soldering. notes this land pattern design is a calculated value based on jeita et - 7501. p lease take into consideration in an actual substrate design about enough the ease of mounting, the intensity of connection, the density of mounting, and the solder paste used, etc the optimal land pattern size changes with these parameters. please use the value shown by the land pattern as reference data.
thc63lvd r 84c_rev.1.20_e copyright?201 6 thine electronics, inc. 15 thine electronics, inc. security e notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know - how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permiss ion is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applications: audio - video device, office automation device, communication device, consumer electronics, smartphone, feature phone , and amusement machine dev ice. this product must not be used for applications that require extremely high - reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of iso/ts16949 ("the specified product") in this data sheet. t hine electronics, inc. (thine) accepts no liability whatsoever for any product other than the specified product for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the spe cified product only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi - conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this pr oduct is not designed to be radiation - proof. 8. testing and other quality control techniques are used to this product to the extent thine deems necessary to support warranty for performance of this product . except where mandated by applicable law or deemed n ecessary by thine based on the user s request, testing of all functions and performance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. 10. the product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. the damage may ca use a smoking and ignition. therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. thine electronics, inc. sales@thine.co.jp

▲Up To Search▲

Price & Availability of THC63LVDM83D

	To Download THC63LVDM83D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .